The present invention relates in general to computer system operation and more particularly to a method and apparatus for handling interrupts at a memory node controller without attached processors in a computer system.
In a conventional multi-processor computer system, multiple node controllers are connected by an interconnection network and communicate among each other, over such network. Each node controller manages memory in a region of the computer system""s address space, interfaces with attached processors, provides a port to communicate with attached input/output devices, and includes a network interface to provide communications with the interconnection network. There may be computer system designs and applications that may require only modest amounts of computational power and thus some node controllers may not have processors attached to them. Node controllers without attached processors provide memory capacity and input/output bandwidth for processors located elsewhere in the computer system.
When a node controller detects an anomalous event or an error that requires handling, the normal course of action is to signal an interrupt condition to a processor attached to the node controller. The processor will then service the interrupt, handle the error situation, and restore the computer system to a normal state. However, an anomalous event may occur at a node controller that does not have an attached processor. Therefore, it is desirable to provide a technique to handle an interrupt condition at a node controller that is not coupled to a processor.
From the foregoing, it may be appreciated that a need has arisen for a technique to handle interrupts at a node controller without an attached processor. In accordance with the present invention, a method and apparatus for handling interrupts at a memory node controller without attached processors in a computer system are provided that substantially eliminate or reduce disadvantages and problems associated with conventional computer systems.
According to an embodiment of the present invention there is provided a memory node controller without attached processors for handling interrupts that includes a processor interface unit that receives an interrupt signal associated with an interrupt condition. The processor interface unit determines whether the interrupt signal is to be forwarded. The processor interface unit forwards the interrupt signal in response to a determination that the interrupt signal is to be forwarded. An input/output interface unit receives the interrupt signal from the processor interface unit. The input/output interface unit generates an interrupt request in response to the interrupt signal for transfer to a remote node controller. The remote node controller includes a processor that can process the interrupt condition.
The present invention provides various technical advantages over conventional computer system operation. For example, one technical advantage is to provide an ability to handle errors that occur in a node controller without an attached processor. Another technical advantage is to forward an interrupt condition from a node controller without an attached processor to a remote node controller that has a processor capable of handling the interrupt condition. Yet another technical advantage is to identify a remote node controller that can handle the interrupt condition. Other technical advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.